Conserving resources, including energy, has become a pre-eminent objective in today's world. Manufacturers of electronic circuits, and especially ICs, are sensitive to the need to improve the energy efficiency of their products. Given the ever-decreasing size of transistors (e.g., complementary metal-oxide semiconductor field-effect transistors) in modern ICs, leakage power has become a major source of inefficiency. Therefore, a variety of techniques are being pursued to reduce leakage power. One way to reduce leakage power is to raise transistor threshold voltage, or Vt. However, since Vt and transistor switching speed bear a generally inverse relationship, raising Vt slows overall IC performance. Thus Vt cannot be raised indiscriminately.
For this reason, EDA tools have recently been introduced that use structural static timing analysis (STA) to identify critical paths (the longest and therefore the most speed-sensitive logic paths) in an IC. The EDA tools then raise the Vt of only the transistors that lie outside of those critical paths. This solution, called “multi-Vt optimization,” is proving effective at reducing leakage power without sacrificing IC speed.